Digital lock detector for phase-locked loop
US7676014B2 · kind B2 · utility
5Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Oct 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.