Duration minimum and maximum circuit for performance counter
US7676530B2 · kind B2 · utility
3Cited by
50References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2004 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Jul 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for tracking the minimum and maximum duration of an event of interest is described. The circuit is connected to a counter for counting a number of clock cycles that the event of interest is active and comprises logic for detecting deactivation of the event of interest and generating a duration end signal; logic responsive to the duration end signal for comparing a count value with a shadow value; and logic for updating the shadow value based on results of the comparing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.