Enhanced floating-point unit for extended functions
US7676535B2 · kind B2 · utility
4Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Sep 28, 2005 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Jan 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5355
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a technique to perform floating-point operations. A floating-point (FP) squarer squares a first argument to produce an intermediate argument. The first and intermediate arguments have first and intermediate mantissas and exponents. A FP multiply-add (MAD) unit performs a multiply-and-add operation on the intermediate argument, a second argument, and a third argument to produce a result having a result mantissa and a result exponent. The second and third arguments have second and third mantissas and exponents, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.