Compact instruction set encoding
US7676653B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Mar 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30178
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a decode unit for decoding instructions in a processor. The decode unit comprises opcode decoding logic, operand decoding logic, and a sixteen-bit input. The opcode decoding logic is operable to determine an opcode using five bits of the input and the operand decoding logic is operable to determine three four-bit operand elements from the remaining eleven bits of the input, the three operand elements each having one of twelve possible binary values. The operand decoding logic is operable to decode an encoded group of the eleven bits to determine a first part of each of the three operand elements, and to read verbatim a verbatim group of the eleven bits to determine a second part of each of the three operand elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.