Method for improving the data transfer in semi synchronous clock domains integrated circuits at any possible m/n clock ratio
US7676685B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Oct 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for data transfer between two semi-synchronous clock domains in a System on Chip (SoC) includes first and second integrated processors or circuits respectively operating at first and second clock frequencies. The SoC includes a phase for detecting, for each frequency ratio between the first and second clock frequencies, a maximum rate of the data transfer, with the rate being a function of all the possible input and output delays supported by the SoC. This is dependent on the parameters of the SoC. There is also a phase for programming a generic frequency converter between the first and second integrated processors for the data transfer, and a phase for scheduling the data transfer between the semi-synchronous clock domains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.