Semiconductor device having symbol pattern utilized as identification sign
US7679202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2007 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.