Programmable interconnect structures
US7679399B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2008 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Feb 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes.A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits.A method of forming a programmable interconnect structure for an integrated circuit comprises: fabricating one or more pass-gates on a substrate layer to electrically connect two …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.