Method and apparatus for tuning delay
US7679414B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2008 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Jul 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide a fine tunable digital delay circuit that can be applied in a high frequency digital circuit. Further, the digital delay circuit can utilize a level restoring technique to enable a wide tunable delay range. The delay circuit can include a delay element configured to receive an input signal at an input node and output a controlled signal having a controlled rise time and a controlled fall time at a controlled node, a first plurality of transistors configured to bias a supply node of the delay element to govern the controlled rise time of the controlled signal, and a second plurality of transistors configured to bias a ground node of the delay element to govern the controlled fall time of the controlled signal. The delay circuit can further include a restoring circuit configured to charge or discharge the controlled node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.