Digital input class-D amplifier
US7679435B2 · kind B2 · utility
10Cited by
5References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 14, 2008 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Mar 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/808
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital input class-D amplifier includes a decoder which outputs a plurality of lines of time-series digital signals having a density of 1 or 0 conforming to an input digital signal, an error integrator which integrates a difference between a drive waveform to be applied to a load and a sum of the plurality of lines of time-series digital signals output from the decoder, and a modulation circuit which generates a pulse modulated with a pulse width or a pulse density based on a result of integration performed by the error integrator. The load is driven in accordance with the pulse generated by the modulation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.