Amplifier arrangement and method
US7679452B2 · kind B2 · utility
12Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2006 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Jul 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier arrangement having a transistor arrangement comprising a first transistor (1) in common-emitter configuration and a second transistor (2) in common-base configuration. A switching device (7) couples, in a first mode of operation, the first transistor (1) to an input (3) of the amplifier arrangement and while the second transistor (2) forms a cascade stage. In a second mode of operation the second transistor (2) is coupled to the input (3). While high gain is achieved during the first mode, the second mode allows for high linearity without requiring inductive degeneration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.