Optimized buffer loading for packet header processing
US7680116B1 · kind B1 · utility
5Cited by
32References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2007 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Mar 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/602
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processing engine for processing header data includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When the L2 and L3 header generation units finish processing a data unit, the data unit may be unloaded from the first and second buffer while a new data unit is simultaneously loaded to the header processing engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.