Frame mapping scheduler for scheduling data blocks using a mapping table and a weight table
US7680124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2004 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Sep 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/026
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network processor or other processing device of a communication system includes scheduling circuitry configured to schedule data blocks for transmission from a plurality of users or other transmission elements in timeslots of a frame. The scheduling circuitry utilizes a weight table and a mapping table. The weight table comprises a plurality of entries, with each of the entries identifying a particular one of the transmission elements. The mapping table comprises at least one entry specifying a mapping between a particular timeslot of the frame and an entry of the weight table. The scheduling circuitry determines a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry and utilizing a resultant value to access the weight table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.