Communications chip having a plurality of logic analysers
US7680142B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2004 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Aug 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communications chip having a plurality of ports. Each port is provided with an interface for attachment to an external communications facility to exchange data traffic. There is also a switching matrix for routing data traffic on the chip between the ports. The chip further includes a plurality of logic analyzers. Each logic analyzer is associated with a corresponding one of the ports. Each logic analyzers is operable to monitor data traffic passing through its corresponding port and to trigger on one or more predetermined conditions relating to the monitored data traffic. The chip further includes a control interface to allow reconfiguration of the predetermined conditions for at least one of the logic analyzers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.