PCR jitter reduction in a VSB and/or EVSB multiplexer system
US7680155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2003 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Oct 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/242
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Program clock references in first and second MPEG data streams are re-stamped in accordance with delays introduced into the first and second MPEG data streams. Accordingly, the program clock references in the first MPEG data stream are re-stamped according to a variable delay in the first MPEG data stream, and the program clock references in the second MPEG data stream are re-stamped according to a variable delay in the second MPEG data stream. The re-stamped program clock references in the second MPEG data stream are corrected according to a fixed delay in the second MPEG data stream. The first and second MPEG data streams are multiplexed, and the multiplexed first and second MPEG data streams are transmitted and received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.