Method and apparatus for signal phase locking
US7680234B2 · kind B2 · utility
8Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2004 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Dec 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/53806
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) circuit provides ac devices, such as power inverters and power measurement devices, with a reliable means for synchronizing to ac electrical systems. In an exemplary embodiment, the PLL circuit is configured for operation with single-phase electrical systems and offers substantial noise immunity by basing its locking operations on measured fundamental components, i.e., measured x-y phasors, of the electrical system voltage. Further, with its phasor-based locking operations and with its timer/counter-based operation, the PLL circuit can be implemented partly or wholly in digital processing logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.