Memory interface including generation of timing signals for memory operation
US7680966B1 · kind B1 · utility
13Cited by
43References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2004 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Jan 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes an interface controller for communication with a semiconductor device over a communication link. A clock signal is transmitted from the semiconductor device over the link to the memory device. A frequency of the clock signal may be any within a given range of frequencies. A frequency value signal conveying the value of the frequency of the clock signal is also transmitted. The interface controller includes circuitry for deriving from the clock signal and from the frequency value signal at least one timing signal for any operation in the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.