Page and block management algorithm for NAND flash
US7680977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2007 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Aug 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.