Sub-page-granular cache coherency using shared virtual memory mechanism
US7680987B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2006 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Jan 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique involves providing access to shared data based on enhanced standard virtual memory mechanisms. Once data from a shared area of memory is moved into primary memory of a first computerized device from a second computerized device, the first computerized device can retain that data in order to shorten the latency of subsequent accesses. Such a technique can be configured to handle shared data at the sub-page-granular level using sparse virtual pages to minimize memory access contention and thus improve the likelihood of quick re-hits. Furthermore, such a technique can be conveniently accomplished through an enhancement to a common page fault handler of an operating system and utilizing atomic remote access support from a standard communications protocol thus alleviating the need to employ more costly and complicated solutions such as inflexible hardware implementations or independent programs that could pose additional design burdens and reliability concerns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.