Computer sleep/awake circuit
US7681059B2 · kind B2 · utility
1Cited by
2References
13Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Aug 4, 2006 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Jun 3, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sleep/awake circuit includes an infrared receiving/sending module, a micro-control circuit, and a bus control circuit. The micro-control circuit sends a command signal to the infrared receiving/sending module at predetermined intervals. The infrared receiving/sending module detects the presence or absence of a user and then sends a signal back to the micro-control circuit indicating a result. According to the result, the micro-control circuit exchanges data and clock signals with the bus control circuit. The bus control circuit then sends control signals to the computer to control sleep/awake states of the computer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.