Method and system for a message processor switch for performing incremental redundancy in edge compliant terminals
US7681065B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 2004 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Jul 11, 2028 |
Classification
- Technology area (CPC D)Textiles; Paper
- CPC primaryD04B21/14
- WIPO fieldTextile and paper machines
- WIPO sectorMechanical engineering
Abstract
Certain embodiments of the invention may be found in a method and system for processing messages. Aspects of the method may comprise receiving at least one signal on a chip that controls switching from a core processor to a DSP. At least a first bus that couples the core processor to a message processor and at least a first clock signal that clocks the core processor may be switched. At least a second bus that couples the DSP to the message processor and at least a second clock signal that clocks the DSP may be switched. When a loss of clock signal from the core processor or the DSP to the message processor is detected, a third clock signal for clocking the message processor may be generated. The message processor switch significantly reduces the amount of bandwidth utilized for transfer of data between the core processor and the DSP and provides incremental redundancy (IR) without high hardware cost and software MIPS, thereby providing significant improvement in system performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.