Method and apparatus for improved error avoidance in a redundant data path system
US7681082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Mar 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A logic arrangement, method and computer program for reducing incidence of errors in a redundant path system during a process of attachment of a device to a running subsystem, comprises a control component for encapsulating the process of attachment of a device to a running subsystem; a disabling component for disabling a path interface; a testing component for testing for the presence of a usable data path across at least one further path interface; and an enabling component for enabling the at least one further path interface to accept communication with the device responsive to a positive outcome from the testing component; wherein the control component is adapted to permit operation after attachment of the device only if full redundancy is retained. A re-enabling component may re-enable any path interface or further path interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.