Semiconductor memory module with error correction

US7681108B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Karl-Heinz Moosrainer · Birkenfeld, DE
• Srdjan Djordjevic · Munich, DE
• Michael Bestele · Lappersdorf, DE

Key dates

• Filing date: Jul 19, 2006
• Grant date: Mar 16, 2010
• Expiry date: Jan 13, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P70/50
• WIPO field: Audio-visual technology
• WIPO sector: Electrical engineering

Abstract

A semiconductor memory module comprises a control chip for driving ECC memory chips and further memory chips. The memory chips are arranged in two rows on a top side and a bottom side of the module circuit board. The ECC memory chips are arranged centrally on the module circuit board alongside the rows of the memory chips. A control bus connects the ECC memory chips and also the memory chips to the control chip. In a region remote from the control chip, the control bus branches in a contact-making hole into a first partial bus, to which a first group of memory chips are connected, and a second partial bus, to which a second group of memory chips are connected. The ECC memory chips are likewise connected to the control bus via the contact-making hole. Since the ECC memory chips are not arranged directly under the control chip, a bus branch directed backward is not required. As a result, space considerations on the module circuit board are eased and signal integrity on the control buses is improved.