Method of error correction in MBC flash memory
US7681109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2006 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Nov 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.