Method and apparatus for register allocation in presence of hardware constraints

US7681187B2 · kind B2 · utility

Assignee

• NVIDIA Corporation · US

Inventors

• Michael Ludwig · Mannheim, DE
• Jayant B. Kolhe · Milpitas, US
• Robert Steven Glanville · Cupertino, US
• Geoffrey Carlton BERRY · San Francisco, US
• Boris Beylin · Palo Alto, US
• Michael Bunnell · Pleasanton, US

Key dates

• Filing date: Mar 31, 2005
• Grant date: Mar 16, 2010
• Expiry date: Sep 30, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/005
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and apparatus for optimizing register allocation during scheduling and execution of program code in a hardware environment. The program code can be compiled to optimize execution given predetermined hardware constraints. The hardware constraints can include the number of register read and write operations that can be performed in a given processor pass. The optimizer can initially schedule the program using virtual registers and a goal of minimizing the amount of active registers at any time. The optimizer reschedules the program to assign the virtual registers to actual physical registers in a manner that minimizes the number of processor passes used to execute the program.