Method of adaptively selecting chips for reducing in-line testing in a semiconductor manufacturing line
US7682842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2008 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Aug 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2894
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.