Method and device for producing layout patterns of a semiconductor device having an even wafer surface
US7682880B2 · kind B2 · utility
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10References
5Claims
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Key dates
| Filing date | Mar 14, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Mar 14, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.