Method for reducing pillar structure dimensions of a semiconductor device
US7682942B2 · kind B2 · utility
4Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jan 28, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist layer is then etched away to provide a photoresist pattern to create the pillar structures. The photoresist pattern is processed in the layer of photoresist after the step of exposing the layer of photoresist and prior to the step of etching to reduce the dimensions of the photoresist pattern in the layer of photoresist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.