Integrated circuits with jitter-reducing balancing logic
US7683659B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2008 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jun 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.