Fully differential amplifier with continuous-time offset reduction
US7683717B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2005 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Dec 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45681
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Fully differential amplifier circuits are described herein that set the common mode voltage as well as reduce the output offset voltage (offset cancellation). A circuit according to one embodiment includes a first section for generating first and second output signals on first and second outputs from first and second input signals, a first negative feedback loop coupled to the first section, and a second negative feedback loop coupled to the first section. A second section controls the first negative feedback loop for adjusting the first output signal towards a common mode voltage level, and for reducing an offset voltage of the first output signal in different loop bandwidths. A third section controls the second negative feedback loop for adjusting the second output signal towards the common mode voltage level, and for reducing an offset voltage of the second output signal in different loop bandwidths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.