Pattern matching apparatus
US7683812B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2006 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Dec 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/042
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This invention relates to a pattern recognition correlator implemented entirely in the electronic domain. The correlator has a serial to parallel conversion means to convert input serial binary data into at least one input parallel binary electrical signal and a comparator to compare the or each input parallel data signal with a reference parallel binary data signal. The serial to parallel conversion means may comprises a demultiplexer to effectively slow the data update rate and a series of latch circuits to provide the parallel data signal. The comparator may be arranged to perform bit addition and may be arranged such that a zero total sum is an indication of correlation. The bit addition may be performed b an array of logic gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.