Low latency communication via memory windows
US7685319B2 · kind B2 · utility
1Cited by
7References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2004 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Nov 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L61/25
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.