Direct memory access controller
US7685331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2006 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Aug 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct memory access controller (DMAC) is disclosed. In one case, the DMAC is configured to manage a DMA transmission of mass data with non-continuous addresses with a nonvolatile memory. The DMAC has to transmit them in batches according to their respective continuous addresses but, different from the prior art systems, does not interrupt a CPU for each batch of the DMA transmissions. In a DMA transmission between a functional device and the nonvolatile memory, a central processor configures a link-list of cluster addresses, which is obtained from a FAT (i.e., a file allocated table) in the nonvolatile memory and may be non-continuous, in a logic address buffer. Then, a divide unit provided in the DMAC divides a non-continuous link-list of cluster addresses from the logic address buffer into a plurality of continuous sub-link-list of cluster addresses, thus the DMAC can configure each batch of DMA transmission according to the continuous sub-link-list of cluster addresses without causing impact on the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.