Hardware memory management unit simulation using concurrent lookups for address translation data
US7685355B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 7, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Nov 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various technologies and techniques are disclosed for concurrently performing address translation data lookups for use by an emulator. On a first thread, a first lookup is performed for address translation data for use by an emulator. On a second thread, a second lookup for the address translation data is concurrently and speculatively performed. The address translation data from a successful lookup from either the first lookup or the second lookup is used to map a simulated physical address to a virtual address of the emulator. For example, the first thread can perform a translation lookaside buffer lookup while the second thread concurrently and speculatively performs a page table entry lookup for the address translation data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.