Alternating fault tolerant reconfigurable computing architecture
US7685464B2 · kind B2 · utility
3Cited by
15References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2006 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Aug 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing radiation effects in an electronic circuit is disclosed. The method involves periodically transferring operation of the electronic circuit to at least one alternate processing element of a plurality of processing elements. With the at least one alternate processing element in control, the method reconfigures one or more processing elements of the plurality of processing elements. Once the one or more processing elements are reconfigured, the method synchronizes the one or more processing elements with the at least one alternate processing element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.