Data system simulated event and matrix debug of pipelined processor
US7685467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2006 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Nov 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.