LDPC decoder
US7685502B2 · kind B2 · utility
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4References
6Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 22, 2005 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jul 31, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1105
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An LDPC decoder has a determined number of processing units operating in parallel. Storage circuitry contains first words having a juxtaposition of a first type of message. The storage circuitry also contains second words having a juxtaposition of a second type of message. A message provision unit provides each processing unit with the messages. A message write unit may write words into the storage circuitry in a way that depends on the contents of the words. The message provision unit may provide data in a way that depends on the contents of the words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.