High density memory device manufacturing using isolated step pads
US7687921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2008 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Oct 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device includes multiple IC dies stacked in an offset stacking arrangement on a substrate. Each IC die includes electrically isolated step pads that facilitates transmitting a dedicated signal between a (beginning) substrate bonding pad and a selected (terminal) contact pad of any die by way of short bonding wires that extend up the stack between the electrically isolated step pads. A memory devices includes stacked memory IC die, wherein “shared” signal transmission paths are formed by associated bonding wires that link corresponding contact pads of each memory die, and dedicated select/control signals are transmitted to each memory die by separate transmission paths formed in part by associated electrically isolated step pads. Substrate space overhung by the stack is used for passive components and IC dies. Memory controller die may be mounted on the stack and connected by dedicated transmission paths utilizing the electrically isolated step pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.