Multilayer chip capacitor
US7688568B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2009 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Mar 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilayer chip capacitor includes: a capacitor body having a plurality of dielectric layers laminated therein and comprising first and second capacitor units; and first to fourth external electrodes formed on an outer surface of the capacitor body, wherein the first capacitor unit comprises first and second internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the first and second external electrodes, and having different polarities, each pair of first and second internal electrodes being laminated one or more times to discriminate a plurality of capacitors with a certain capacitance, the second capacitor unit comprises third and fourth internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the third and fourth external electrodes, and having the same polarities as those of the first and second internal electrodes, each pair of third and fourth internal electrodes being laminated one or more times to discriminate one or more capacitors each with a certain capacitance, and at least three capacitors included in the first and second capacitor units have different capacitances or resonance…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.