Nonvolatile semiconductor memory capable of trimming an initial program voltage for each word line
US7688632B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Jul 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory of the present invention includes a plurality of bit lines and word lines which are arranged to intersect each other; a memory cell array having a plurality of electrically-programmable memory cells arranged in a region in which the bit lines and the word lines intersect; a trimming circuit configured to obtain a parameter of an initial program voltage for each word line of the plurality of word lines; an initial Vpgm parameter register configured to receive the parameter of the initial program voltage from the trimming circuit and to store the parameter; and a control circuit configured to perform programming of data to the memory cell array based on the parameter of the initial program voltage stored in the initial Vpgm parameter register, the trimming circuit being arranged in a part of the control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.