Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages
US7688669B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 11, 2008 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Sep 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.