Duty cycle counting phase calibration scheme of an input/output (I/O) interface
US7688928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2006 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Dec 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment a control unit of a communication system exchanging a multiple-phase time-interleaved data includes a first Phase-Locked Loop (PLL) to generate a set of un-calibrated multiple-phase signals of a first-clock; a second-PLL, a pulse generator, a pulse-width measurement unit and a phase calibration engine to evaluate adjustments required in a temporal location of a logically critical voltage transition edge in each signal in the un-calibrated set; and a phase adjustment unit to adjust the temporal location of the logically critical voltage transition edge in each signal in the un-calibrated set to generate a set of calibrated multiple-phase signals of the first-clock such that each signal in the calibrated set includes the logically critical voltage transition edge which is time skewed in a predetermined amount from the logically critical voltage transition edge in other signals in the same set within a predetermined accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.