All-digital phase modulator/demodulator using multi-phase clocks and digital PLL
US7688929B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Oct 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase rotator, which selects one clock phase from a bank of multi-phase clocks. The multi-phase clocks have the same frequency, but are offset in phase from each other. An output divider divides the selected multi-phase clock to generate a phase-modulated output. A feedback divider divides a fixed-phase clock from the multi-phase clocks to generate the feedback clock. An analog or a digital front-end may be used to convert analog inputs to digital signals to increment or decrement the counter, or to encode multiple digital bits as phase assignments. For a de-modulator, a digital-to-analog converter (DAC) or a digital decoder produces the final output from the count of the up/down counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.