Method and system for reducing pin count in an integrated circuit when interfacing to a memory
US7689763B2 · kind B2 · utility
4Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Nov 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a system and method for reducing pin count in an integrated circuit (IC) when interfacing to a synchronous dynamic random access memory (SDRAM). The SDRAM has a plurality of address lines and a plurality of data lines. The method includes connecting together the plurality of data lines and the plurality of address lines. The IC interfaces to the SDRAM through the connected plurality of address lines and the plurality of data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.