Power-performance modulation in caches using a smart least recently used scheme
US7689772B2 · kind B2 · utility
7Cited by
7References
24Claims
0Family size
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Key dates
| Filing date | May 4, 2006 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Apr 23, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.