Mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multi-processor computing system
US7689856B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 2006 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Jan 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0012
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multiprocessor computing system. A stream of data is transferred from a first clock domain with a first clock signal to a second clock domain with a second clock signal. The first and second clock signals have a mesochronous relationship. The first clock signal is sampled in the second clock domain. In response to the sampling of the first clock signal, a modified version of the first clock signal is formed having a known phase relationship to the second clock signal. A parallel form of the received data is formed under the control of modified version of the first clock signal. In response to the sampling of the first clock signal, a subset of contiguous bits of the parallel data is selected for use in the second clock domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.