High-performance FET device layout
US7689946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2006 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Oct 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast FET and a method and system for designing the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.