Nanowire device with (111) vertical sidewalls and method of fabrication
US7692179B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2004 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Jul 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/81
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A nano-scale device and method of fabrication provide a nanowire having (111) vertical sidewalls. The nano-scale device includes a semiconductor-on-insulator substrate polished in a [110] direction, the nanowire, and an electrical contact at opposite ends of the nanowire. The method includes wet etching a semiconductor layer of the semiconductor-on-insulator substrate to form the nanowire extending between a pair of islands in the semiconductor layer. The method further includes depositing an electrically conductive material on the pair of islands to form the electrical contacts. A nano-pn diode includes the nanowire as a first nano-electrode, a pn-junction vertically stacked on the nanowire, and a second nano-electrode on a (110) horizontal planar end of the pn-junction. The nano-pn diode may be fabricated in an array of the diodes on the semiconductor-on-insulator substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.