Package using array capacitor core
US7692284B2 · kind B2 · utility
2Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2005 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Jan 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0156
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a technique to fabricate a package substrate. The package substrate includes top substrate layers, an array capacitor, and bottom substrate layers. The top substrate layers embed micro-vias. The micro-vias have a micro-via area and provide electrical connections between the top substrate layers. The array capacitor structure is placed in contact with the micro-via area. The array capacitor structure is electrically connected to the micro-vias. The bottom substrate layers are formed on the array capacitor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.