Configuring structured ASIC fabric using two non-adjacent via layers
US7692309B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 6, 2007 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Nov 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
Abstract
An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a first non-customized metal routing layer, a customized via layer, and a second non-customized metal routing layer, is disposed on top of the plurality of non-customized layers. A second routing grid, which includes a third non-customized metal routing layer, another customized via layer, and a fourth non-customized metal routing layer, is disposed above the first routing grid. A non-customized via layer is disposed above the first routing grid and beneath the second routing grid. The routing grids and the non-customized via layer collectively facilitate routing connections to and from the logic cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.