Sense amplifier based flip-flop
US7692466B2 · kind B2 · utility
419Cited by
3References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Nov 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to generate a first and second output signal based on the clock signal and the first and second input signals. The delay stage is operatively coupled to the input and output stages. The delay stage includes a first and second branch. The second branch includes at least one more delay element than the first branch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.